SOC in its own way
From its introduction in the 1990s, the SoC has gone through many phases. Early SoCs consisted of a processing engine, some SRAM, and lots of random, or glue, logic. The glue logic defined the SoC's specific functionality, differentiating it from ASSP chips for a particular application. Current SoCs comprise one or more processing blocks (microprocessors and/or DSP engines), communication cores, memory blocks (SRAM, DRAM, flash, or other), random logic, and, often, analog functions. SoCs may also contain graphic or other application-specific cores. As was the case for earlier SoCs, designers use glue logic to connect the cores to make the SoC meet a set of design specifications.
The siren song of SoC design is a chip that combines high performance with minimum silicon area, which translates to low cost. The obstacles to SoC design are high development cost (NRE), high design complexity, and long development time. The combination of these feature sets makes today's SoCs attractive for high volume, high-complexity system design, but not for low-to-middle volume applications. Another barrier to SoC design is the cost of redoing the design if first silicon is tested and found to not meet specifications. A design error or specification change due, for example, to a change in a communication standard, can result in a very expensive silicon re-spin (new masks and a new process run). A 0.18-micron mask set runs around $250,000, a cost which, when added to the delay needed to fabricate new silicon, can result in a loss of millions of dollars in potential product revenue.
The New Kid on the SoC Block CSoCs add something new to the SoC mix—a configurable fabric that designers can manipulate, after chip fabrication, to achieve specific functionality. Configurability lets you change on-chip functions for a variety of reasons. These reasons include a change in a CSoC's core functionality; compatibility with a change in a communications or other standard to which the CSoC must conform; and correcting a design error incurred during original chip development. Post-process configurability also lets you more easily generate derivative products from the original chip design, as well as create products that can adapt to changing requirements.
posted by interconnect @ 11:22 PM
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